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git01.mediatek.com / filogic / uboot / cb0da87fc4aeac8c98f34ae7779730a801b0f493 / cpu / ppc4xx / 4xx_ibm_ddr2_autocalib.c
  1. cb9ebd0 ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling by Stefan Roese · Mon Sep 28 17:33:45 2009 +0200
  2. f1a2ed8 ppc4xx: Autocalibration can set RDCC to over aggressive value. by Adam Graham · Mon Feb 09 13:18:12 2009 -0800
  3. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  4. 89caad9 ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change by Adam Graham · Mon Oct 06 10:16:13 2008 -0700
  5. a7c7d86 Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)" by Stefan Roese · Mon Sep 22 11:06:50 2008 +0200
  6. 97d6a34 ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB) by Victor Gallardo · Tue Sep 16 06:59:13 2008 -0700
  7. ee8e0cf ppc4xx: IBM Memory Controller DDR autocalibration routines by Adam Graham · Wed Sep 03 12:26:28 2008 -0700