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git01.mediatek.com / filogic / uboot / cad56718089e0cf5f1fb7d398c70454ea1f4d45e / board / xilinx / zynq / zynq-zc706
  1. accb63b WS cleanup: remove excessive empty lines by Wolfgang Denk · Mon Sep 27 17:42:37 2021 +0200
  2. 3fd6633 WS cleanup: remove trailing empty lines by Wolfgang Denk · Mon Sep 27 17:42:36 2021 +0200
  3. 79c1f6d arm: zynq: Remove low level UART setting by Michal Simek · Fri Dec 06 09:33:25 2019 +0100
  4. 70df9d6 SPDX: Convert a few files that were missed before by Tom Rini · Mon May 07 17:02:21 2018 -0400
  5. 322b57b arm: zynq: Convert all board to use arch ps7_init code by Michal Simek · Fri Nov 10 11:00:42 2017 +0100
  6. 3924efd arm: zynq: Remove ps7_debug code by Michal Simek · Fri Nov 10 09:09:48 2017 +0100
  7. 3917c4f ARM: zynq: Simplify zynq configuration by Michal Simek · Fri May 20 14:59:33 2016 +0200