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git01.mediatek.com / filogic / uboot / ca70805e8a0bb17b4f799f5194d8ad426598f2be / arch / arm / dts / socfpga_cyclone5_sr1500.dts
  1. feaa3f9 dts: cadence_spi: Sync DT bindings with Linux by Jason Rush · Tue Jan 23 17:13:10 2018 -0600
  2. 72887e3 arm: socfpga: Fix typos in DT files (environmnet -> environment) by Stefan Roese · Mon Apr 18 14:22:04 2016 +0200
  3. 85e8439 arm: socfpga: sr1500: Misc updates (SPI speed, env location) by Stefan Roese · Thu Mar 03 16:57:39 2016 +0100
  4. bf5ed2e arm: socfpga: Add SoCFPGA SR1500 board by Stefan Roese · Wed Nov 18 11:06:09 2015 +0100