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git01.mediatek.com / filogic / uboot / c83e7f9ce8972ad393c6a9fc0deda9f111ad49f0 / board / freescale / imx8mp_evk / lpddr4_timing.c
  1. c83e7f9 imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit by Jian Li · Thu Feb 27 09:40:10 2020 +0800
  2. 742b1eb imx8mp: DDR performance tunning by Jian Li · Mon Jan 20 15:14:42 2020 +0800
  3. 6f27594 imx8mp: enable rd_port_urgent by Jian Li · Wed Jan 08 10:14:16 2020 +0800
  4. c47e09d imx: add i.MX8MP EVK board by Peng Fan · Mon Dec 30 17:46:21 2019 +0800