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git01.mediatek.com / filogic / uboot / c6bfdc2b4a754fcd59c3d5258d1f13456cc18cd4 / arch / arm / mach-imx / imx8ulp / clock.c
  1. 8840830 imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock by Ye Li · Fri Oct 29 09:46:30 2021 +0800
  2. 23ee0e1 imx8ulp: clock: Support to enable/disable the ADC1 clock by Alice Guo · Fri Oct 29 09:46:29 2021 +0800
  3. cb7e375 imx8ulp: clock: Support to reset DCNano and MIPI DSI by Ye Li · Fri Oct 29 09:46:27 2021 +0800
  4. 328f201 imx8ulp: clock: Reset DDR controller before clock enable by Ye Li · Fri Oct 29 09:46:26 2021 +0800
  5. 27666ca imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display by Ye Li · Fri Oct 29 09:46:21 2021 +0800
  6. 3d3dfb0 imx8ulp: clock: Add MIPI DSI clock and DCNano clock by Ye Li · Fri Oct 29 09:46:19 2021 +0800
  7. da0469d imx8ulp: clock: Support LPAV clocks in cgc and pcc by Ye Li · Fri Oct 29 09:46:18 2021 +0800
  8. 690eea1 arm: imx8ulp: add clock support by Peng Fan · Sat Aug 07 16:00:45 2021 +0800
  9. b15705a arm: imx: basic i.MX8ULP support by Peng Fan · Sat Aug 07 16:00:35 2021 +0800