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git01.mediatek.com / filogic / uboot / c66c950e1c9158ee516ade743915caabe7b16287 / arch / riscv
  1. c66c950 riscv: support building double-float modules by Heinrich Schuchardt · Wed Oct 12 14:59:51 2022 +0200
  2. 43e1f93 riscv: Fix build against binutils 2.38 by Alexandre Ghiti · Mon Oct 03 18:07:54 2022 +0200
  3. 2e4938b dm: core: Drop ofnode_is_available() by Simon Glass · Tue Sep 06 20:27:17 2022 -0600
  4. df00afa treewide: Drop bootm_headers_t typedef by Simon Glass · Tue Sep 06 20:26:50 2022 -0600
  5. eff2077 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next by Tom Rini · Mon Sep 26 11:27:30 2022 -0400
  6. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  7. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  8. 4f4f583 board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · Fri Sep 09 17:32:40 2022 +0200
  9. ebe3b23 riscv: dts: sifive: Synchronize FU740 and Unmatched DT by Icenowy Zheng · Thu Aug 25 16:11:19 2022 +0800
  10. 13d7170 dt-bindings: clock: sifive: sync FU740 PRCI clock binding header by Icenowy Zheng · Thu Aug 25 16:11:18 2022 +0800
  11. f781746 riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux by Jessica Clarke · Fri Aug 12 18:50:03 2022 +0100
  12. 4150eec riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · Wed Jun 01 10:01:49 2022 +0800
  13. 66ae7fe riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · Fri May 20 14:41:17 2022 +0300
  14. 8aaae3d zynqmp: Run board_get_usable_ram_top() only on main U-Boot by Ashok Reddy Soma · Thu Jul 07 10:45:37 2022 +0200
  15. c65d29f arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED by Michal Simek · Thu Jul 07 10:47:16 2022 +0200
  16. 94b4fec Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig by Tom Rini · Sat Jun 25 11:02:46 2022 -0400
  17. 5a9095c linker_lists: Rename sections to remove . prefix by Andrew Scull · Mon May 30 10:00:04 2022 +0000
  18. 4ddbade Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · Wed May 25 12:16:03 2022 -0400
  19. 53a442a riscv: Clean up asm/io.h by Leo Yu-Chi Liang · Thu May 19 16:43:31 2022 +0800
  20. 7a35171 riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h by Michal Simek · Wed May 18 12:54:01 2022 +0200
  21. ea14390 riscv: alloc space exhausted by Heinrich Schuchardt · Tue Apr 05 16:47:15 2022 +0200
  22. f4b4d75 riscv: provide missing base extension functions by Heinrich Schuchardt · Thu Mar 17 07:36:14 2022 +0100
  23. 295e1ce cmd: sbi: add Performance Monitoring Unit Extension by Heinrich Schuchardt · Wed Mar 16 21:21:18 2022 +0100
  24. 9442f15 Merge tag 'v2022.04-rc5' into next by Tom Rini · Mon Mar 28 12:36:49 2022 -0400
  25. 5b845a4 k210: dts: align plic node with Linux by Niklas Cassel · Tue Mar 01 10:35:42 2022 +0000
  26. b2c0bb4 k210: dts: align fpioa node with Linux by Damien Le Moal · Tue Mar 01 10:35:41 2022 +0000
  27. 0a876d7 k210: dts: add missing power bus clocks by Damien Le Moal · Tue Mar 01 10:35:40 2022 +0000
  28. 6e5a8b7 k210: use the board vendor name rather than the marketing name by Damien Le Moal · Tue Mar 01 10:35:39 2022 +0000
  29. fc55736 event: Convert arch_cpu_init_dm() to use events by Simon Glass · Fri Mar 04 08:43:05 2022 -0700
  30. c8481ef dts: automatically build necessary .dtb files by Rasmus Villemoes · Mon Jan 10 14:34:41 2022 +0100
  31. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  32. f263479 efi_loader: fix SectionAlignment, FileAlignment by Heinrich Schuchardt · Fri Jan 14 21:40:15 2022 +0100
  33. f0106d4 riscv: revert Complete efi header for RV32/64 by Heinrich Schuchardt · Sun Jan 09 18:16:11 2022 +0100
  34. bd07fb4 riscv: qemu: Split devicetree files for qemu_riscv32/64 by Simon Glass · Thu Dec 16 20:59:12 2021 -0700
  35. 9b9c4d5 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · Wed Nov 24 14:32:10 2021 -0800
  36. f50fad6 riscv: Support booting SiFive Unmatched from SPI. by Thomas Skibo · Wed Nov 24 14:32:09 2021 -0800
  37. b56e2fd riscv: dts: Split Microchip device tree by Padmarao Begari · Wed Nov 17 18:21:17 2021 +0530
  38. 2f5b807 riscv: add #define in asm/io.h for some device drivers by Wei Fu · Sun Oct 24 00:31:12 2021 +0800
  39. 69c681e riscv: function to retrieve SBI implementation version by Heinrich Schuchardt · Mon Oct 25 15:09:34 2021 +0200
  40. 579f12b riscv: Avoid io read/write cause wrong result by Nick Hu · Mon Oct 18 11:50:05 2021 +0800
  41. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  42. bedc439 fdtdec: Support reserved-memory flags by Thierry Reding · Fri Sep 03 15:16:21 2021 +0200
  43. 5e33691 fdtdec: Support compatible string list for reserved memory by Thierry Reding · Fri Sep 03 15:16:19 2021 +0200
  44. 85c057e image: Drop IMAGE_ENABLE_OF_LIBFDT by Simon Glass · Sat Sep 25 19:43:21 2021 -0600
  45. 2795bf2 riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · Thu Sep 23 10:34:29 2021 +0800
  46. cc382ff sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · Sun Sep 12 21:11:46 2021 +0200
  47. 2d1c651 riscv: add missing SBI extension definitions by Heinrich Schuchardt · Sun Sep 12 21:11:44 2021 +0200
  48. c7ad952 riscv: Fix setting no-map in reserved memory nodes by Samuel Holland · Sun Sep 12 11:05:47 2021 -0500
  49. 637fa28 lmb: riscv: Add arch_lmb_reserve() by Marek Vasut · Fri Sep 10 22:47:15 2021 +0200
  50. 17a2907 Merge tag 'v2021.10-rc4' into next by Tom Rini · Thu Sep 16 10:29:40 2021 -0400
  51. b28d6b9 riscv: lib: modify the indent by Zong Li · Wed Sep 01 15:01:43 2021 +0800
  52. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  53. c39544c riscv: lib: implement enable_caches for sifive cache by Zong Li · Wed Sep 01 15:01:41 2021 +0800
  54. a33070c common: board_r: support enable_caches for RISC-V by Zong Li · Wed Sep 01 15:01:40 2021 +0800
  55. 79c6855 riscv: show code leading to exception by Heinrich Schuchardt · Sat Sep 04 10:36:49 2021 +0200
  56. 4b198e3 Kconfig: Remove all default n/no options by Michal Simek · Fri Aug 27 08:48:10 2021 +0200
  57. 3ef67ae Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig by Tom Rini · Thu Aug 26 11:47:59 2021 -0400
  58. f1ac8fa riscv: cpu: fu740: Fix typo of date by Zong Li · Mon Aug 02 15:34:14 2021 +0800
  59. 5629aaa efi_loader: add Linux magic to RISC-V crt0 by Heinrich Schuchardt · Fri May 28 22:24:37 2021 +0200
  60. bccfc2e i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · Sat Jul 10 21:14:36 2021 -0600
  61. 288ad1f board: sifive: drop stuff related to unmatched revision 1 by Zong Li · Tue Jul 20 14:26:08 2021 +0800
  62. 51744fe riscv: booti: do not force relocation if force_reloc is not set by Vitaly Wool · Tue Apr 06 10:50:16 2021 +0300
  63. babf1cb riscv: dts: add OpenPiton RISC-V board dts support by Tianrui Wei · Wed Jul 07 15:48:22 2021 +0800
  64. bab770a riscv: dts: add dts for unmatched rev1 by Zong Li · Wed Jun 30 23:23:49 2021 +0800
  65. dab3e8e board: sifive: Add an interface to get PCB revision by Zong Li · Wed Jun 30 23:23:48 2021 +0800
  66. 9627a8e riscv: sifive: fu740: Support i2c in spl by Zong Li · Wed Jun 30 23:23:47 2021 +0800
  67. 3376055 riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · Wed Jun 30 23:23:46 2021 +0800
  68. 2ef594d board: riscv: add openpiton-riscv64 SoC support by Tianrui Wei · Thu Jul 01 12:54:19 2021 +0800
  69. d3e8b73 Merge tag 'v2021.07-rc5' into next by Tom Rini · Mon Jun 28 16:22:13 2021 -0400
  70. e6638b4 k210: dts: Set PLL1 to the same rate as PLL0 by Sean Anderson · Fri Jun 11 00:16:15 2021 -0400
  71. b6ec26b riscv: andes_plic: Fix riscv_get_ipi() mask by Bin Meng · Tue Jun 15 13:45:57 2021 +0800
  72. 2114b47 riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config by Bin Meng · Fri Jun 04 13:51:13 2021 +0800
  73. 85741a2 riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit by Bin Meng · Fri Jun 04 13:51:12 2021 +0800
  74. cd00421 riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes by Bin Meng · Fri Jun 04 13:51:11 2021 +0800
  75. 996068b riscv: ae350: dts: Remove the unnecessary space in bootargs by Bin Meng · Fri Jun 04 13:51:10 2021 +0800
  76. c907594 riscv: ae350: dts: Add SPDX license header by Bin Meng · Fri Jun 04 13:51:09 2021 +0800
  77. 26190b8 riscv: cpu: fu740: clear feature disable CSR by Green Wan · Thu May 27 06:52:14 2021 -0700
  78. 2e5da52 board: sifive: add HiFive Unmatched board support by Green Wan · Thu May 27 06:52:13 2021 -0700
  79. e552af3 riscv: dts: add SiFive Unmatched board support by Green Wan · Thu May 27 06:52:12 2021 -0700
  80. 06a3e40 riscv: dts: add fu740 support by Green Wan · Thu May 27 06:52:11 2021 -0700
  81. ecefa5f drivers: clk: add fu740 support by Green Wan · Thu May 27 06:52:08 2021 -0700
  82. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · Thu May 27 06:52:07 2021 -0700
  83. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · Thu May 20 13:23:52 2021 +0200
  84. 442d446 riscv: Drop USE_SPL_FIT_GENERATOR by Bin Meng · Mon May 10 20:23:41 2021 +0800
  85. 6b977a4 riscv: ae350: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:40 2021 +0800
  86. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:39 2021 +0800
  87. eada910 riscv: dts: Sort build targets in alphabetical order by Bin Meng · Mon May 10 20:23:38 2021 +0800
  88. ced2097 riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:35 2021 +0800
  89. ce64bd3 riscv: Group assembly optimized implementation of memory routines into a submenu by Bin Meng · Thu May 13 16:46:18 2021 +0800
  90. 8a27fcd riscv: Fix memmove and optimise memcpy when misalign by Bin Meng · Thu May 13 16:46:17 2021 +0800
  91. ac95f46 riscv: Fix arch_fixup_fdt always failing without /chosen by Sean Anderson · Fri May 14 22:36:16 2021 -0400
  92. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  93. b1b3bc0 Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · Mon May 10 17:08:16 2021 +0800
  94. 72422b9 riscv: Don't reserve AI ram in k210 dts by Sean Anderson · Thu Apr 08 22:13:13 2021 -0400
  95. b23d757 riscv: k210: Use AI as the parent clock of aisram, not PLL1 by Sean Anderson · Thu Apr 08 22:13:12 2021 -0400
  96. 7be6d2b riscv: k210: Rename airam to aisram by Sean Anderson · Thu Apr 08 22:13:11 2021 -0400
  97. e8d9e3a riscv: Enable some devices pre-relocation by Sean Anderson · Thu Apr 08 22:13:09 2021 -0400
  98. 968a13f riscv: cpu: fu740: clear feature disable CSR by Green Wan · Sun May 02 23:23:05 2021 -0700
  99. 2612080 riscv: cpu: Add callback to init each core by Green Wan · Sun May 02 23:23:04 2021 -0700
  100. d62063d lmb: move CONFIG_LMB in Kconfig by Patrick Delaunay · Wed Mar 10 10:16:25 2021 +0100