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git01.mediatek.com / filogic / uboot / c4cc97985bbfd0cf073ccf36c1e6e7c3fcb9d48d / drivers / clk / clk_k210.c
  1. 1a3427b clk: treewide: switch to clock dump from clk_ops by Igor Prusov · Thu Nov 09 13:55:15 2023 +0300
  2. 10ceddf clk: k210: Move soc_clk_dump function by Igor Prusov · Thu Nov 09 13:55:11 2023 +0300
  3. 9576a3b clk_k210.c: Clean up how we handle nop by Tom Rini · Thu Oct 26 14:31:36 2023 -0400
  4. 495e80f Correct SPL uses of CMD_CLK by Simon Glass · Sun Feb 05 15:36:26 2023 -0700
  5. 135e5f6 k210: fix k210_pll_calc_config() by Heinrich Schuchardt · Sun Oct 16 18:12:32 2022 +0200
  6. 6e5a8b7 k210: use the board vendor name rather than the marketing name by Damien Le Moal · Tue Mar 01 10:35:39 2022 +0000[Renamed (99%) from drivers/clk/clk_kendryte.c]
  7. e72139e clk: k210: Try harder to get the best config by Sean Anderson · Sat Sep 11 13:20:03 2021 -0400
  8. 89c3584 k210: clk: Refactor out_of_spec tests by Sean Anderson · Sat Sep 11 13:20:01 2021 -0400
  9. b0126e9 clk: k210: Fix checking if ulongs are less than 0 by Sean Anderson · Sat Sep 11 13:20:00 2021 -0400
  10. 152919d clk: k210: Move k210 clock out of its own subdirectory by Sean Anderson · Fri Jun 11 00:16:14 2021 -0400[Renamed from drivers/clk/kendryte/clk.c]
  11. 1a37182 clk: k210: Don't set PLL rates if we are already at the correct rate by Sean Anderson · Fri Jun 11 00:16:12 2021 -0400
  12. 3a29bc6 clk: k210: Re-add support for setting rate by Sean Anderson · Fri Jun 11 00:16:11 2021 -0400
  13. ecf9284 clk: k210: Implement soc_clk_dump by Sean Anderson · Fri Jun 11 00:16:10 2021 -0400
  14. edbe849 clk: k210: Move pll into the rest of the driver by Sean Anderson · Fri Jun 11 00:16:09 2021 -0400
  15. 2957313 clk: k210: Rewrite to remove CCF by Sean Anderson · Fri Jun 11 00:16:08 2021 -0400
  16. 95951fc Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next by Tom Rini · Sun Jun 13 07:48:22 2021 -0400