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git01.mediatek.com / filogic / uboot / c2a441cbbe85d81d5104a349bb8fadd8879348c3 / arch / riscv / cpu / andes / Kconfig
  1. 5d0bbea andes: Unify naming policy for Andes related source by Leo Yu-Chi Liang · Tue May 14 17:50:11 2024 +0800[Renamed (91%) from arch/riscv/cpu/andesv5/Kconfig]
  2. 9ae964b riscv: andesv5: Set default cache line size to 64-bytes by Yu Chien Peter Lin · Thu Apr 11 17:29:45 2024 +0800
  3. ac5e68f riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode by Yu Chien Peter Lin · Fri Sep 29 12:03:07 2023 +0800
  4. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800[Renamed from arch/riscv/cpu/ax25/Kconfig]
  5. e440ed4 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:50 2023 +0800
  6. 816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
  7. f9269c7 Prepare v2023.04-rc2 by Tom Rini · Mon Feb 13 18:39:15 2023 -0500