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git01.mediatek.com / filogic / uboot / c0b43cf09b7f4b1d8add8651f86c264f2b81dc48 / include / fsl_esdhc.h
  1. 0244963 fsl_esdhc: Deal with watermark level register related changes by Priyanka Jain · Wed Feb 09 09:24:10 2011 +0530
  2. 5c72f35 ppc/85xx: PIO Support for FSL eSDHC Controller Driver by Dipen Dudhat · Mon Oct 05 15:41:58 2009 +0530
  3. e5853af fsl_esdhc: Only modify the field we are changing in WML by Roy Zang · Tue Feb 09 18:23:33 2010 +0800
  4. b7ef756 fsl_esdhc: Add function to reset the eSDHC controller by Jerry Huang · Thu Mar 18 15:57:06 2010 -0500
  5. 09876a3 fsl_esdhc: Always stop clock before changing frequency by Kumar Gala · Thu Mar 18 15:51:05 2010 -0500
  6. ff7a5ca fsl_esdhc: add support for mx51 processor by Stefano Babic · Fri Feb 05 15:11:27 2010 +0100
  7. 424d73f fsl_esdhc: fix wrong clock mask by Li Yang · Thu Jan 07 16:00:13 2010 +0800
  8. f751a3c fsl_esdhc: Add device tree fixups by Anton Vorontsov · Wed Jun 10 00:25:29 2009 +0400
  9. e52ffb8 Add support for the Freescale eSDHC found on 8379 and 8536 SoCs by Andy Fleming · Thu Oct 30 16:47:16 2008 -0500