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git01.mediatek.com / filogic / uboot / bebd282446306e3adfea2144af472e87856955d8 / arch / riscv / cpu / u-boot.lds
  1. 5e75a27 riscv: Fix breakage caused by linker relaxation by Sean Anderson · Tue Dec 17 21:35:32 2019 -0500
  2. 55bc1bd riscv: Fix clear bss loop in the start-up code by Rick Chen · Thu Nov 14 13:52:27 2019 +0800
  3. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700
  4. c7feb19 riscv: Fix coding style issues in the linker script by Bin Meng · Wed Sep 26 06:55:12 2018 -0700
  5. a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · Wed Sep 26 06:55:11 2018 -0700[Renamed from arch/riscv/cpu/ax25/u-boot.lds]
  6. b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · Mon Aug 20 14:25:49 2018 +0200
  7. 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · Tue Jun 12 07:48:37 2018 +0200
  8. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800[Renamed (96%) from arch/riscv/cpu/nx25/u-boot.lds]
  9. 9677a37 efi_loader: Enable RISC-V support by Rick Chen · Mon May 28 19:06:37 2018 +0800
  10. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  11. e76b804 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · Tue Dec 26 13:55:48 2017 +0800