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git01.mediatek.com / filogic / uboot / be7f13c112cb360cd9e94f1f9d85e9685f2620a8 / include / ddr_spd.h
  1. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · Thu Mar 27 17:54:47 2014 -0700
  2. 4a71741 powerpc: Fix CamelCase warnings in DDR related code by Priyanka Jain · Wed Sep 25 10:41:19 2013 +0530
  3. ec7fbf5 Coding Style cleanup: replace leading SPACEs by TABs by Wolfgang Denk · Fri Oct 04 17:43:24 2013 +0200
  4. 794c692 powerpc/mpc8xxx: Add fine timing support for DDR3 by York Sun · Fri Aug 17 08:22:37 2012 +0000
  5. 09da8b8 mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification by Ira W. Snyder · Mon Nov 21 13:20:33 2011 -0800
  6. 72bdc80 Adding more SPD registers by York Sun · Fri May 27 07:32:50 2011 +0800
  7. 046d772 mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements by Kyle Moffett · Mon Mar 28 11:35:48 2011 -0400
  8. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · Fri Jul 02 22:25:55 2010 +0000
  9. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  10. 5b4da32 Add proper SPD definitions for DDR1/2/3 by James Yang · Tue Aug 26 15:01:27 2008 -0500