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filogic
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uboot
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be7ce26b2980a04f4d25ae3dd7774a1aa593f7ae
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arch
/
arm
/
mach-socfpga
/
include
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mach
/
misc.h
adc079f
arm: socfpga: arria10: Enable double peripheral RBF configuration
by Tien Fong Chee
· Sun Nov 07 23:08:56 2021 +0800
8ca1708
arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF
by Tien Fong Chee
· Sun Nov 07 23:08:55 2021 +0800
61e9199
arm: socfpga: soc64: Check FPGA Config status register before bridge reset
by Chee Hong Ang
· Thu Aug 06 11:56:29 2020 +0800
ea84ae6
socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
by Tom Rini
· Thu May 14 08:30:05 2020 -0400
fed4c95
arm: socfpga: Convert reset manager from struct to defines
by Ley Foon Tan
· Fri Nov 08 10:38:19 2019 +0800
5216671
socfpga: fix include guard in misc.h (arch vs. global)
by Simon Goldschmidt
· Wed Oct 23 22:32:30 2019 +0200
b6ba490
ARM: socfpga: Pull PL310 clearing into common code
by Marek Vasut
· Thu Mar 21 23:05:38 2019 +0100
713a8a2
ARM: socfpga: Add support for selecting bridges in bridge command
by Marek Vasut
· Tue Apr 16 22:28:08 2019 +0200
ff14f16
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
by Ang, Chee Hong
· Wed Dec 19 18:35:15 2018 -0800
da13a0a
arm: socfpga: fix SPL booting from fpga OnChip RAM
by Simon Goldschmidt
· Wed Oct 10 14:55:23 2018 +0200
8fdb419
ARM: socfpga: Reorder Arria10 SPL
by Marek Vasut
· Sat Aug 18 19:11:52 2018 +0200
8b73c87
ARM: socfpga: Zap all the UART handling complexity
by Marek Vasut
· Sun Apr 15 16:29:12 2018 +0200
8e30203
arm: socfpga: gen5: combine some init code for SPL and U-Boot
by Simon Goldschmidt
· Mon Aug 13 21:34:35 2018 +0200
4cc6b58
arm: socfpga: misc: Move bridge command to misc common
by Ley Foon Tan
· Thu May 24 00:17:23 2018 +0800
10e4779
SPDX: Convert all of our single license tags to Linux Kernel style
by Tom Rini
· Sun May 06 17:58:06 2018 -0400
cfd0c54
arm: socfpga: Add misc support for Arria 10
by Ley Foon Tan
· Wed Apr 26 02:44:43 2017 +0800
b149f2b
arm: socfpga: Restructure misc driver
by Ley Foon Tan
· Wed Apr 26 02:44:36 2017 +0800