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git01.mediatek.com / filogic / uboot / bbf245d62d9b61249e076e8c4ee9e4156bd60431 / board / xilinx / zynqmp / zynqmp-zcu102-revA / psu_init_gpl.c
  1. 0c25b27 arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration by Neal Frager · Thu May 05 10:55:51 2022 +0200
  2. aded579 arm64: zynqmp: Remove low level UART setting by Michal Simek · Fri Dec 06 09:12:26 2019 +0100
  3. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  4. d99247d arm64: zynqmp: Add low level initialization for zcu102-revA by Michal Simek · Wed Mar 28 14:47:16 2018 +0200