Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / bbbfe91434c39ca8d4c6fe6dbee15b60969f2d34 / drivers / clk / aspeed / clk_ast2500.c
  1. d7f3789 aspeed: ast2500: fix D2-PLL clock setting in RGMII mode by Cédric Le Goater · Mon Oct 29 07:06:41 2018 +0100
  2. 62b4bfd aspeed: ast2500: fix missing break in D2PLL clock enablement by Cédric Le Goater · Mon Oct 29 07:06:37 2018 +0100
  3. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  4. ba1dea4 dm: Rename dev_addr..() functions by Simon Glass · Wed May 17 17:18:05 2017 -0600
  5. a91f1d2 aspeed: Refactor SCU to use consistent mask & shift by maxims@google.com · Mon Apr 17 12:00:33 2017 -0700
  6. 15016af aspeed: Add support for Clocks needed by MACs by maxims@google.com · Mon Apr 17 12:00:32 2017 -0700
  7. 995167b aspeed: Add P-Bus clock in ast2500 clock driver by maxims@google.com · Mon Apr 17 12:00:29 2017 -0700
  8. adea66c aspeed: Make SCU lock/unlock functions part of SCU API by maxims@google.com · Mon Apr 17 12:00:23 2017 -0700
  9. d067217 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation by maxims@google.com · Mon Jan 30 11:35:04 2017 -0800
  10. 2d5a2ad aspeed: Add basic ast2500-specific drivers and configuration by maxims@google.com · Wed Jan 18 13:44:56 2017 -0800