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git01.mediatek.com / filogic / uboot / bbb20942c9fbb337171582a1600c964321f61e0d / arch / arm / cpu / armv8 / cache_v8.c
  1. e0e9871 armv8: mmu: fix page table mapping by Peng Fan · Tue Nov 28 10:31:28 2017 +0800
  2. 4415c3b arm: Support cache invalidate by Simon Glass · Wed Apr 05 17:53:18 2017 -0600
  3. 5bb14e0 armv8: mmu: Add a function to change mapping attributes by York Sun · Mon Mar 06 09:02:33 2017 -0800
  4. ddb0f63 armv8: add hooks for all cache-wide operations by Stephen Warren · Wed Oct 19 15:18:46 2016 -0600
  5. fa3754e armv8: mmu: Detect page table overflow in emergency pt creation by Alexander Graf · Sat Jul 30 23:13:03 2016 +0200
  6. c7104e5 armv8: mmu: Add support of non-identical mapping by York Sun · Fri Jun 24 16:46:22 2016 -0700
  7. f44afe7 armv8: mmu: split block if necessary by York Sun · Fri Jun 24 16:46:21 2016 -0700
  8. a81fcd1 armv8: mmu: house cleaning by York Sun · Fri Jun 24 16:46:20 2016 -0700
  9. bc78b92 arm64: Fix layerscape mmu setup by Alexander Graf · Mon Mar 21 20:26:12 2016 +0100
  10. bc40da9 arm64: Only allow dcache disabled in SPL builds by Alexander Graf · Fri Mar 04 01:09:55 2016 +0100
  11. ce0a64e arm64: Remove non-full-va map code by Alexander Graf · Fri Mar 04 01:09:54 2016 +0100
  12. 6b3e7ca thunderx: Move mmu table into board file by Alexander Graf · Fri Mar 04 01:09:48 2016 +0100
  13. e317fe8 arm64: Make full va map code more dynamic by Alexander Graf · Fri Mar 04 01:09:47 2016 +0100
  14. f03c0e4 arm64: Disable TTBR1 maps in EL1 by Alexander Graf · Fri Mar 04 01:09:46 2016 +0100
  15. fb74cc1 thunderx: Calculate TCR dynamically by Alexander Graf · Fri Mar 04 01:09:45 2016 +0100
  16. 78eaa49 armv8: New MMU setup code allowing to use 48+ bits PA/VA by Sergey Temerkhanov · Wed Oct 14 09:55:45 2015 -0700
  17. e28e18c armv8/layerscape: Update MMU table with execute-never bits by Alison Wang · Thu Nov 05 11:15:49 2015 +0800
  18. 7333c6a armv8: allow custom MMU setup routines on ARMv8 by Stephen Warren · Mon Oct 05 12:09:00 2015 -0600
  19. a3e45ab armv8/mmu: Set bits marked RES1 in TCR by Thierry Reding · Thu Aug 20 11:52:14 2015 +0200
  20. 7f8e178 armv8: fsl-lsch3: Rewrite MMU translation table entries by Alison Wang · Tue Aug 18 11:22:05 2015 +0800
  21. 2219026 ARM: cache: implement a default weak flush_cache() function by Wu, Josh · Mon Jul 27 11:40:17 2015 +0800
  22. aaa3545 ARM: cache: add an empty stub function for invalidate/flush dcache by Wu, Josh · Mon Jul 27 11:40:16 2015 +0800
  23. ba2432a armv8: caches: Added routine to set non cacheable region by Siva Durga Prasad Paladugu · Fri Jun 26 18:05:07 2015 +0530
  24. 59c364d armv8/cache: Fix page table creation by Thierry Reding · Wed Jul 22 17:10:11 2015 -0600
  25. 1ce575f armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack by York Sun · Tue Jan 06 13:18:42 2015 -0800
  26. a84cd72 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC by York Sun · Mon Jun 23 15:15:54 2014 -0700
  27. ef63194 ARMv8: Adjust MMU setup by York Sun · Mon Jun 23 15:15:53 2014 -0700
  28. ef04201 armv8/cache: Change cache invalidate and flush function by York Sun · Wed Feb 26 13:26:04 2014 -0800
  29. 897947c armv8/cache: Consolidate setting for MAIR and TCR by York Sun · Wed Feb 26 13:26:02 2014 -0800
  30. 85fd5f1 arm64: core support by David Feng · Sat Dec 14 11:47:35 2013 +0800