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git01.mediatek.com / filogic / uboot / bb930c37e23a13287993029a2ff1b5808083eb3f / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c
  1. 0fdbe20 sunxi: Add support for A33 PLL11 (second DRAM pll) by Hans de Goede · 10 years ago
  2. 627bc69 sunxi: Drop pll6 setting from clock_init_uart by Hans de Goede · 10 years ago
  3. 645d4d5 sunxi: Fix PLL1 running at half speed on sun8i by Hans de Goede · 10 years ago
  4. 0bfa774 sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them by Hans de Goede · 10 years ago
  5. 0cbc4cb sun6i: Add a sigma_delta_enable paramter to clock_set_pll5() by Hans de Goede · 10 years ago
  6. 70d7ab5 sunxi: Add video pll clock functions by Hans de Goede · 10 years ago
  7. c27d68d sun6i: Add clock functions needed for SPL / DRAM init by Hans de Goede · 10 years ago
  8. 6ee6388 ARM: sunxi: Add support for using R_UART as console by Chen-Yu Tsai · 10 years ago
  9. 3a04542 ARM: sun6i: Add clock support by Chen-Yu Tsai · 10 years ago