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git01.mediatek.com / filogic / uboot / b999ae84380533d52ad8589d0cbade83ebb72a77 / board / freescale / p1_p2_rdb / ddr.c
  1. 5e35d8a mpc85xx boards: initdram() cleanup/bugfix by Becky Bruce · Fri Dec 17 17:17:56 2010 -0600
  2. 9cd9e13 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz by Poonam Aggrwal · Wed Jun 23 19:32:28 2010 +0530
  3. a417d6b 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate by Poonam Aggrwal · Tue Oct 27 09:36:38 2009 +0530
  4. a4f546d 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB. by Poonam Aggrwal · Tue Oct 27 09:26:55 2009 +0530
  5. dfa652d ppc/85xx: 32bit DDR changes for P1020/P1011 by Poonam Aggrwal · Sat Sep 19 17:50:17 2009 +0530
  6. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  7. 987862c 85xx: Add support for P2020RDB board by Poonam Aggrwal · Wed Aug 05 13:29:24 2009 +0530