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git01.mediatek.com / filogic / uboot / b948810c3c95b01570b7ce3472e451375c122e78 / arch / arm / cpu / armv7 / zynq / slcr.c
  1. 4dded98 net: zynq_gem: Calculate clock dividers dynamically by Soren Brinkmann · Thu Nov 21 13:39:01 2013 -0800
  2. 3b5b992 net: zynq_gem: Move RCLK details out of driver by Soren Brinkmann · Thu Nov 21 13:39:00 2013 -0800
  3. 11704c2 zynq: Add support to find bootmode by Jagannadha Sutradharudu Teki · Thu Jan 09 01:48:21 2014 +0530
  4. 661ccfc zynq: slcr: Wait 100ms till clk is properly setup by Michal Simek · Wed May 08 15:37:28 2013 +0200
  5. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  6. 15d654c fpga: zynq: Add support for loading bitstream by Michal Simek · Mon Apr 22 15:43:02 2013 +0200
  7. d9f2c11 net: gem: Fix gem driver on 1Gbps LAN by Michal Simek · Mon Oct 15 14:01:23 2012 +0200
  8. eb1dfa7 arm: zynq: Add SLCR support with system reset by Michal Simek · Mon Feb 04 12:38:59 2013 +0100