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git01.mediatek.com / filogic / uboot / b834f922390c056b2b97e798c250b0dbc3f9eee0 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  2. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  3. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500