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git01.mediatek.com / filogic / uboot / b83019fad9c57c7310fb05d787f1afd254b77e3f / arch / riscv / dts / k210.dtsi
  1. e6638b4 k210: dts: Set PLL1 to the same rate as PLL0 by Sean Anderson · Fri Jun 11 00:16:15 2021 -0400
  2. 72422b9 riscv: Don't reserve AI ram in k210 dts by Sean Anderson · Thu Apr 08 22:13:13 2021 -0400
  3. b23d757 riscv: k210: Use AI as the parent clock of aisram, not PLL1 by Sean Anderson · Thu Apr 08 22:13:12 2021 -0400
  4. 7be6d2b riscv: k210: Rename airam to aisram by Sean Anderson · Thu Apr 08 22:13:11 2021 -0400
  5. e8d9e3a riscv: Enable some devices pre-relocation by Sean Anderson · Thu Apr 08 22:13:09 2021 -0400
  6. 1c30c0e riscv: Add watchdog bindings for the k210 by Sean Anderson · Wed Mar 10 21:02:21 2021 -0500
  7. 2ddd3e0 riscv: Add device tree bindings for SPI by Sean Anderson · Fri Oct 16 18:57:54 2020 -0400
  8. fd9571a spi: dw: Add SoC-specific compatible strings by Sean Anderson · Fri Oct 16 18:57:50 2020 -0400
  9. d1b3321 riscv: k210: Reduce DMA block size by Sean Anderson · Mon Oct 12 14:18:15 2020 -0400
  10. 6870556 riscv: Add pinmux and gpio bindings for Kendryte K210 by Sean Anderson · Mon Sep 14 11:02:04 2020 -0400
  11. c6d0ef8 riscv: Update Kendryte device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:28 2020 -0400
  12. d11b582 riscv: Add device tree for K210 and Sipeed Maix BitM by Sean Anderson · Wed Jun 24 06:41:23 2020 -0400