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git01.mediatek.com / filogic / uboot / b7afb1128ef5ae06a1e0b2d08a80280ccc2a8fa5 / board / freescale / mpc8544ds / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  3. 573ad30 FSL DDR: Convert MPC8544DS to new DDR code. by Kumar Gala · Tue Aug 26 08:02:30 2008 -0500