Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b75b15b43bd263db16342ad5d91069b90dac32b6 / drivers / ddr / altera / sdram_gen5.c
  1. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  2. aad29ae dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · Thu Dec 03 16:55:21 2020 -0700
  3. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  4. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  5. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  6. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  7. b7b1838 Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm by Tom Rini · Tue Feb 11 10:58:41 2020 -0500
  8. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  9. 6bccacf ddr: altera: Add DDR2 support to Gen5 driver by Marek Vasut · Fri Oct 18 00:22:31 2019 +0200
  10. 8e16b1e common: Move RAM-sizing functions to init.h by Simon Glass · Sat Dec 28 10:45:05 2019 -0700
  11. 3d3a860 arm: socfpga: Convert system manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:20 2019 +0800
  12. e874433 ddr: socfpga: gen5: constify altera_gen5_sdram_ops by Simon Goldschmidt · Wed Oct 23 22:19:37 2019 +0200
  13. 24910c3 arm: socfpga: move gen5 SDR driver to DM by Simon Goldschmidt · Tue Apr 16 22:04:39 2019 +0200
  14. 38fad17 ARM: socfpga: Rename the gen5 sdram driver to more specific name by Tien Fong Chee · Tue Dec 05 15:58:00 2017 +0800[Renamed from drivers/ddr/altera/sdram.c]
  15. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  16. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · Wed Apr 18 13:50:47 2018 -0400
  17. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  18. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · Mon Apr 04 17:52:21 2016 +0200
  19. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · Tue Dec 29 09:38:52 2015 +0100
  20. 6772cd9 ddr: altera: sdram: Make sdram_start and sdram_end into u32 by Marek Vasut · Sat Aug 01 23:12:11 2015 +0200
  21. 9114407 ddr: altera: sdram: Minor cleanup in sdram_get_rule() by Marek Vasut · Sat Aug 01 23:21:23 2015 +0200
  22. 7fce5bc ddr: altera: sdram: Minor cleanup in sdram_set_rule() by Marek Vasut · Sat Aug 01 22:40:48 2015 +0200
  23. b0d848c ddr: altera: sdram: Add missing kerneldoc by Marek Vasut · Sat Aug 01 22:28:30 2015 +0200
  24. 116d88f ddr: altera: sdram: Clean up sdram_write_verify() by Marek Vasut · Sat Aug 01 22:26:11 2015 +0200
  25. 1796a09 ddr: altera: sdram: Clean up sdram_calculate_size() part 2 by Marek Vasut · Sat Aug 01 21:47:16 2015 +0200
  26. 6d6fbba ddr: altera: sdram: Clean up sdram_calculate_size() part 1 by Marek Vasut · Sat Aug 01 21:44:00 2015 +0200
  27. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200
  28. 1b1cc10 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 by Marek Vasut · Sat Aug 01 22:25:29 2015 +0200
  29. 5a4e8ed ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7 by Marek Vasut · Sat Aug 01 22:03:48 2015 +0200
  30. b81f11c ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6 by Marek Vasut · Sat Aug 01 21:26:55 2015 +0200
  31. 1e271e4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5 by Marek Vasut · Sat Aug 01 21:24:31 2015 +0200
  32. 71c1a00 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4 by Marek Vasut · Sat Aug 01 21:21:21 2015 +0200
  33. 3a07911 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3 by Marek Vasut · Sat Aug 01 21:16:20 2015 +0200
  34. 7697ff7 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2 by Marek Vasut · Sat Aug 01 20:58:44 2015 +0200
  35. 4fccfa4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1 by Marek Vasut · Sat Aug 01 20:39:46 2015 +0200
  36. 4f3adbf ddr: altera: sdram: Introduce socfpga_sdram_config() structure by Marek Vasut · Sat Aug 01 20:30:10 2015 +0200
  37. 92e8e6f ddr: altera: sdram: Clean up set_sdr_mp_threshold() by Marek Vasut · Sat Aug 01 20:14:11 2015 +0200
  38. 44f09cc ddr: altera: sdram: Clean up set_sdr_mp_pacing() by Marek Vasut · Sat Aug 01 20:12:31 2015 +0200
  39. b933b19 ddr: altera: sdram: Clean up set_sdr_mp_weight() by Marek Vasut · Sat Aug 01 20:10:23 2015 +0200
  40. f904a86 ddr: altera: sdram: Clean up set_sdr_fifo_cfg() by Marek Vasut · Sat Aug 01 20:04:33 2015 +0200
  41. 9d64f19 ddr: altera: sdram: Clean up set_sdr_static_cfg() by Marek Vasut · Sat Aug 01 20:04:19 2015 +0200
  42. 820b0d9 ddr: altera: sdram: Clean up set_sdr_addr_rw() by Marek Vasut · Sat Aug 01 19:50:56 2015 +0200
  43. 6e9af9b ddr: altera: sdram: Clean up set_sdr_dram_timing*() by Marek Vasut · Sat Aug 01 19:45:24 2015 +0200
  44. 82a2764 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() by Marek Vasut · Sat Aug 01 19:33:40 2015 +0200
  45. 724c50f ddr: altera: sdram: Clean up compute_errata_rows() part 2 by Marek Vasut · Sat Aug 01 19:20:19 2015 +0200
  46. 186880e ddr: altera: sdram: Clean up compute_errata_rows() part 1 by Marek Vasut · Sat Aug 01 18:54:34 2015 +0200
  47. 2fda506 ddr: altera: sdram: Switch to generic_hweight32() by Marek Vasut · Sat Aug 01 18:46:55 2015 +0200
  48. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  49. 452d639 ddr: altera: Fix typo in mp_threshold1 programming by Marek Vasut · Thu Jul 09 01:47:56 2015 +0200
  50. e08c559 ddr: altera: Move struct sdram_prot_rule prototype by Marek Vasut · Sun Jul 26 10:37:54 2015 +0200
  51. 43bb47e arm: socfpga: Move sdram_config.h to board dir by Marek Vasut · Sun Jul 12 15:59:10 2015 +0200
  52. 429642c driver/ddr/altera: Add DDR driver for Altera's SDRAM controller by Dinh Nguyen · Tue Jun 02 22:52:48 2015 -0500