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git01.mediatek.com / filogic / uboot / b0615a6c4eb21e0407b958a15e8ec19450ecd653 / arch / arm / mach-sunxi / clock_sun50i_h6.c
  1. 964a86f sunxi: clock: H6: Adjust PLL LDO before clock setup by Jernej Skrabec · Sun Jan 30 15:27:15 2022 +0100
  2. 5922114 sunxi: clock: H6/H616: Add resistor calibration by Jernej Skrabec · Sun Jan 30 15:27:14 2022 +0100
  3. e04cd49 sunxi: prcm: Add a few registers by Jernej Skrabec · Sun Jan 30 15:27:13 2022 +0100
  4. 0f7c8bc sunxi: clock: H6/H616: Fix PLL clock factor encodings by Andre Przywara · Wed May 05 13:53:05 2021 +0100
  5. 70bdefa sunxi: spl: Fix H616 clock initialization by Jernej Skrabec · Mon Feb 01 18:25:57 2021 +0100
  6. 8b2239c sunxi: introduce support for H616 clocks by Jernej Skrabec · Mon Jan 11 21:11:40 2021 +0100
  7. 55a30a2 sunxi: Add support for I2C on H6 like SoCs by Jernej Skrabec · Mon Jan 11 21:11:38 2021 +0100
  8. d1fa87d sunxi: add clock code for H6 by Icenowy Zheng · Sat Jul 21 16:20:26 2018 +0800