Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / adf3abdacb5f95793fc784e7c280f01fc275fbe5 / drivers / ddr / altera / sequencer.h
  1. 324d3f7 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL by Marek Vasut · Sun Aug 02 19:24:12 2015 +0200
  2. 32d813e ddr: altera: sequencer: Zap VFIFO_SIZE by Marek Vasut · Sun Aug 02 19:21:56 2015 +0200
  3. 2dfc76b ddr: altera: sequencer: Pluck out RW_MGR_* macros from code by Marek Vasut · Sun Aug 02 18:44:06 2015 +0200
  4. 42ed1f2 ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS by Marek Vasut · Sun Aug 02 18:40:27 2015 +0200
  5. eb98b38 ddr: altera: sequencer: Zap unused params and macros by Marek Vasut · Sun Aug 02 18:27:21 2015 +0200
  6. 0f0840d ddr: altera: Clean up mem_config() by Marek Vasut · Fri Jul 17 01:57:41 2015 +0200
  7. cd5d38e ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly by Marek Vasut · Sun Jul 12 20:49:39 2015 +0200
  8. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  9. a334010 ddr: altera: Pluck out remaining sdr_get_addr() calls by Marek Vasut · Sun Jul 12 19:03:33 2015 +0200
  10. 135cc7f driver/ddr/altera: Add the sdram calibration portion by Dinh Nguyen · Tue Jun 02 22:52:49 2015 -0500