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git01.mediatek.com / filogic / uboot / ad935232e041ff370f75501892cac27c353a53e7 / drivers / clk / uniphier
  1. 9e34de5 clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock by Masahiro Yamada · 8 years ago
  2. 8bdfe0a clk: uniphier: rework UniPhier clk driver by Masahiro Yamada · 8 years ago
  3. c3a29fe clk: uniphier: allow to have clock node under syscon node by Masahiro Yamada · 8 years ago
  4. f18559e clk: uniphier: move U_BOOT_DRIVER entry to core code by Masahiro Yamada · 8 years ago
  5. 630c99f clk: uniphier: constify clock data arrays/structures by Masahiro Yamada · 8 years ago
  6. fa1f73f ARM: uniphier: use (devm_)ioremap() instead of map_sysmem() by Masahiro Yamada · 8 years ago
  7. a962243 clk: convert API to match reset/mailbox style by Stephen Warren · 8 years ago
  8. dcfbfab clk: uniphier: add Media I/O clock driver support for PH1-LD11 by Masahiro Yamada · 9 years ago
  9. 763023c clk: uniphier: add Media I/O clock driver support for PH1-LD20 by Masahiro Yamada · 9 years ago
  10. 46a624f clk: uniphier: use devm_get_addr() to get base address by Masahiro Yamada · 9 years ago
  11. e4dfb05 clk: uniphier: add Media I/O clock driver for UniPhier SoCs by Masahiro Yamada · 9 years ago