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git01.mediatek.com / filogic / uboot / aa65f3d8908bb204ca365d09e6cb8fb7421de145 / arch / arm / mach-socfpga / clock_manager_arria10.c
  1. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  2. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  3. 2669591 arm: socfpga: Convert clock manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:21 2019 +0800
  4. 8fdb419 ARM: socfpga: Reorder Arria10 SPL by Marek Vasut · Sat Aug 18 19:11:52 2018 +0200
  5. 71b1637 ARM: socfpga: clk: Convert to clock framework by Marek Vasut · Mon Aug 06 21:42:05 2018 +0200
  6. fd6bcb5 ARM: socfpga: clk: Drop unused variables on Arria10 by Marek Vasut · Tue Jul 31 17:33:42 2018 +0200
  7. e1dcd62 ARM: socfpga: clk: Obtain handoff base clock via DM by Marek Vasut · Mon Jul 30 15:56:19 2018 +0200
  8. ec472e0 ARM: socfpga: Sync A10 clock manager binding parser by Marek Vasut · Sat May 12 00:09:21 2018 +0200
  9. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  10. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · Wed Apr 18 13:50:47 2018 -0400
  11. 7473932 SOCFPGA: clock manager: implement dw_spi_get_clk function by Eugeniy Paltsev · Thu Dec 28 15:09:02 2017 +0300
  12. ca40f29 arm: socfpga: Add clock driver for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:39 2017 +0800