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git01.mediatek.com / filogic / uboot / a950f1a2eac1a1e6b534724412dbf3ff6d388bdb / drivers / clk / clk-composite.c
  1. 46c8190 clk: Check that composite clock's div has set_rate() by Igor Prusov · Wed Dec 06 02:23:33 2023 +0300
  2. 8767e79 clk: define LOG_CATEGORY for generic and ccf clocks by Patrick Delaunay · Fri Nov 19 15:12:07 2021 +0100
  3. 283dadf clk: cosmetic: reorder include files by Patrick Delaunay · Fri Nov 19 15:12:06 2021 +0100
  4. 46e5f61 clk: Return -ENOSYS when system call is not available by Simon Glass · Thu Mar 25 10:26:09 2021 +1300
  5. 1a62dc1 clk: set flags in the ccf registration routines by Dario Binacchi · Mon Apr 13 14:36:27 2020 +0200
  6. aa1e85f clk: Check that ops of composite clock components exist before calling by Sean Anderson · Wed Jun 24 06:41:07 2020 -0400
  7. cfc2f02 clk: Always use the supplied struct clk by Sean Anderson · Wed Jun 24 06:41:06 2020 -0400
  8. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  9. 2d9bd93 clk: add composite clk support by Peng Fan · Wed Jul 31 07:01:54 2019 +0000