Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a4b3dedeb971e6dfee4e6b0be61368d086534979 / drivers / clk / uniphier
  1. 9e34de5 clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock by Masahiro Yamada · Sat Jan 28 06:53:41 2017 +0900
  2. 8bdfe0a clk: uniphier: rework UniPhier clk driver by Masahiro Yamada · Mon Oct 17 22:18:01 2016 +0900
  3. c3a29fe clk: uniphier: allow to have clock node under syscon node by Masahiro Yamada · Thu Sep 22 07:42:22 2016 +0900
  4. f18559e clk: uniphier: move U_BOOT_DRIVER entry to core code by Masahiro Yamada · Thu Sep 22 07:42:21 2016 +0900
  5. 630c99f clk: uniphier: constify clock data arrays/structures by Masahiro Yamada · Thu Sep 22 07:42:20 2016 +0900
  6. fa1f73f ARM: uniphier: use (devm_)ioremap() instead of map_sysmem() by Masahiro Yamada · Tue Jul 19 21:56:13 2016 +0900
  7. a962243 clk: convert API to match reset/mailbox style by Stephen Warren · Fri Jun 17 09:44:00 2016 -0600
  8. dcfbfab clk: uniphier: add Media I/O clock driver support for PH1-LD11 by Masahiro Yamada · Tue May 24 21:14:02 2016 +0900
  9. 763023c clk: uniphier: add Media I/O clock driver support for PH1-LD20 by Masahiro Yamada · Thu Apr 21 14:43:21 2016 +0900
  10. 46a624f clk: uniphier: use devm_get_addr() to get base address by Masahiro Yamada · Thu Mar 24 22:32:39 2016 +0900
  11. e4dfb05 clk: uniphier: add Media I/O clock driver for UniPhier SoCs by Masahiro Yamada · Tue Feb 02 21:11:32 2016 +0900