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git01.mediatek.com / filogic / uboot / a4a2912434b417b6eb6611b1e1fa884004717cdb / drivers / clk / altera
  1. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  2. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  3. 9d0731d dm: core: remove the duplicated function dm_ofnode_pre_reloc by Patrick Delaunay · Fri Apr 03 11:39:18 2020 +0200
  4. f54b71e clk: socfpga: Read the clock parent's register base in probe function by Chee Hong Ang · Mon Mar 09 01:21:59 2020 -0700
  5. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  6. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  7. ef5458f clk: agilex: Add clock driver for Agilex by Ley Foon Tan · Wed Nov 27 15:55:22 2019 +0800
  8. acdb7af clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_reloc by Patrick Delaunay · Wed Mar 20 18:21:25 2019 +0100
  9. c826a09 clk: Remove DM_FLAG_PRE_RELOC flag in various drivers by Bin Meng · Wed Oct 24 06:36:29 2018 -0700
  10. d6e53c7 drivers: cosmetic: Convert SPDX license tags to Linux Kernel style by Patrick Delaunay · Fri Oct 26 09:02:52 2018 +0200
  11. 3f9d735 clk: socfpga: Add initial Arria10 clock driver by Marek Vasut · Tue Jul 31 17:58:07 2018 +0200