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git01.mediatek.com / filogic / uboot / a473057268d9e0b13ed7754f6fa9ab731fe4878c / arch / arm / mach-zynq / cpu.c
  1. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · Thu Nov 14 12:57:37 2019 -0700
  2. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  3. f7ae6d6 arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO by Michal Simek · Wed Feb 28 09:50:07 2018 +0100
  4. f31d90f arm: zynq: Rework FPGA initialization by Michal Simek · Wed Jan 17 10:56:22 2018 -0300
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. e67c6c4 zynq: Move zynq to clock framework by Stefan Herbrechtsmeier · Tue Jan 17 16:27:30 2017 +0100
  7. 04cfea5 arch, board: squash lines for immediate return by Masahiro Yamada · Tue Sep 06 22:17:38 2016 +0900
  8. 43246cc ARM: zynq: move SoC sources to mach-zynq by Masahiro Yamada · Mon Mar 16 16:43:22 2015 +0900[Renamed from arch/arm/cpu/armv7/zynq/cpu.c]
  9. 0d2fa42 ARM: zynq: Remove empty line by Michal Simek · Tue Jan 13 15:54:04 2015 +0100
  10. ac679ae ARM: zynq: Enable the Neon instructions by Michal Simek · Fri Jan 23 09:45:12 2015 +0100
  11. e26ef3b ARM: zynq: Added efuse status register base address by Siva Durga Prasad Paladugu · Fri Nov 29 19:01:25 2013 +0530
  12. e60148d zynq: Add support for U-BOOT SPL by Michal Simek · Tue Jan 14 14:21:52 2014 +0100
  13. 102ad00 zynq: Provide a framework to read clock frequencies by Soren Brinkmann · Thu Nov 21 13:38:54 2013 -0800
  14. 6026411 zynq: Enable dcache support by Michal Simek · Fri Jan 03 09:32:35 2014 +0100
  15. eea89aa arm: zynq : Revert TZ_DDR_RAM to secure. by Radhey Shyam Pandey · Fri Sep 27 16:52:57 2013 +0530
  16. 9dc81ec arm: zynq: Do not remap OCM to high address by Michal Simek · Wed Aug 28 08:26:41 2013 +0200
  17. d1a428f zynq: Use arch_cpu_init() instead of lowlevel_init() by Michal Simek · Thu Aug 22 14:52:02 2013 +0200
  18. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  19. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  20. 6d46480 arm: zynq: Add lowlevel initialization to C by Michal Simek · Mon Feb 04 12:42:25 2013 +0100
  21. eb1dfa7 arm: zynq: Add SLCR support with system reset by Michal Simek · Mon Feb 04 12:38:59 2013 +0100
  22. dea68a7 arm: Support new Xilinx Zynq platform by Michal Simek · Thu Sep 13 20:23:35 2012 +0000