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git01.mediatek.com / filogic / uboot / a3782b1197d19ea5f0ee4e9de53507cca525976a / arch / riscv / cpu / andes / cache.c
  1. eb422ba andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND by Leo Yu-Chi Liang · Tue May 28 20:57:50 2024 +0800
  2. 5d0bbea andes: Unify naming policy for Andes related source by Leo Yu-Chi Liang · Tue May 14 17:50:11 2024 +0800[Renamed (89%) from arch/riscv/cpu/andesv5/cache.c]
  3. b6b9900 riscv: Remove common.h usage by Tom Rini · Thu Oct 12 19:03:59 2023 -0400
  4. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800[Renamed from arch/riscv/cpu/ax25/cache.c]
  5. b2ccd1c riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:49 2023 +0800
  6. 816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
  7. f9269c7 Prepare v2023.04-rc2 by Tom Rini · Mon Feb 13 18:39:15 2023 -0500