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git01.mediatek.com / filogic / uboot / a243fb291cb146b6afc45bcec1f7a663b45d1aef / drivers / clk / qcom / clock-qcom.h
  1. 9726810 clk/qcom: sdm845: enable SDCC2 core clock by Caleb Connolly · Tue Apr 09 20:03:04 2024 +0200
  2. 78672c6 clk/qcom: add driver for sm8250 GCC by Caleb Connolly · Mon Apr 08 15:06:51 2024 +0200
  3. e55fb90 clk/qcom: add driver for qcm2290 GCC by Caleb Connolly · Mon Apr 08 15:06:49 2024 +0200
  4. cbdad44 clk/qcom: use offsets for RCG registers by Caleb Connolly · Wed Apr 03 14:07:40 2024 +0200
  5. aae4649 clk: qcom: add support for power domains uclass by Volodymyr Babchuk · Mon Mar 11 21:33:45 2024 +0000
  6. 397c84f clk/qcom: fix rcg divider value by Caleb Connolly · Tue Nov 07 12:41:05 2023 +0000
  7. fbacc67 clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() by Caleb Connolly · Tue Nov 07 12:41:04 2023 +0000
  8. 10a0abb clk/qcom: use function pointers for enable and set_rate by Caleb Connolly · Tue Nov 07 12:41:03 2023 +0000
  9. 7a63294 clk/qcom: sdm845: add register map for simple gate clocks by Caleb Connolly · Tue Nov 07 12:41:02 2023 +0000
  10. 6c0b844 clk/qcom: handle resets and clocks in one device by Konrad Dybcio · Tue Nov 07 12:41:01 2023 +0000
  11. 878b26a clk/qcom: move from mach-snapdragon by Caleb Connolly · Tue Nov 07 12:40:59 2023 +0000[Renamed from arch/arm/mach-snapdragon/clock-snapdragon.h]
  12. a3e804d clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0 by Sumit Garg · Wed Feb 01 19:28:57 2023 +0530
  13. 038f2b9 clocks: qcom: add clocks for SDM845 debug uart by Dzmitry Sankouski · Sun Oct 17 13:44:30 2021 +0300
  14. ae29977 mach-snapdragon: Fix UART clock flow by Ramon Fried · Wed May 16 12:13:39 2018 +0300
  15. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  16. 92c1eff arm: mach-snapdragon: refactor clock driver by Jorge Ramirez-Ortiz · Wed Jan 10 11:33:49 2018 +0100