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git01.mediatek.com / filogic / uboot / a0e86db8a45b65b3c40b6f6b306b4bf279ce7122 / cpu / mpc8xxx / ddr / options.c
  1. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  2. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
  3. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  4. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  5. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  6. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  7. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500