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git01.mediatek.com / filogic / uboot / a06d74c6ca19a67bafd0948ba2d6b13c32a3181f / board / freescale / mpc8641hpcn / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  2. 82f15f3 Coding Style cleanup, update CHANGELOG by Wolfgang Denk · Sun Nov 02 16:14:22 2008 +0100
  3. 4e0dd7f Add DDR options setting on MPC8641HPCN board by Haiying Wang · Fri Oct 03 12:37:57 2008 -0400
  4. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  5. cad506c FSL DDR: Convert MPC8641HPCN to new DDR code. by Kumar Gala · Tue Aug 26 15:01:35 2008 -0500