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git01.mediatek.com / filogic / uboot / a06d74c6ca19a67bafd0948ba2d6b13c32a3181f / board / freescale / mpc8560ads / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  3. 99d5071 FSL DDR: Convert MPC8560ADS to new DDR code. by Jon Loeliger · 17 years ago