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git01.mediatek.com / filogic / uboot / a03908e7edaf8c888eece5945ab5bdb25ef6fd40 / board / freescale / mpc8544ds / ddr.c
  1. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · 14 years ago
  2. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · 14 years ago
  3. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  4. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  5. 573ad30 FSL DDR: Convert MPC8544DS to new DDR code. by Kumar Gala · 16 years ago