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git01.mediatek.com / filogic / uboot / 9e36b82964bc60914e5fbb1c16ca6866ba4cce9f / board / freescale / p1_p2_rdb
  1. 9e36b82 ppc/85xx: Clean up use of LAWAR defines by Kumar Gala · Sat Sep 19 11:20:54 2009 -0500
  2. 584fae5 ppc/85xx: Clean up p1_p2_rdb PCI setup by Kumar Gala · Thu Sep 03 10:09:04 2009 -0500
  3. 6472af8 ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address by Kumar Gala · Wed Sep 09 11:40:41 2009 -0500
  4. 666ced1 ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host by Kumar Gala · Wed Sep 02 09:03:08 2009 -0500
  5. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  6. f857ed9 85xx: Added PCIe support for P1 P2 RDB by Poonam Aggrwal · Fri Aug 21 07:29:58 2009 +0530
  7. 2cca63f 85xx: Move to a common linker script by Kumar Gala · Fri Aug 07 13:00:55 2009 -0500
  8. 987862c 85xx: Add support for P2020RDB board by Poonam Aggrwal · Wed Aug 05 13:29:24 2009 +0530