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git01.mediatek.com / filogic / uboot / 9dba262eb2637bd37ceb36b2abc125341d0aec49 / arch / arm / dts / socfpga_cyclone5_sr1500.dts
  1. 64a12bf arm: socfpga: gen5: add reset & sdr node to SPL devicetrees by Simon Goldschmidt · Fri Mar 01 20:12:29 2019 +0100
  2. a009fa7 dts: switch spi-flash to jedec, spi-nor compatible by Neil Armstrong · Sun Feb 10 10:16:20 2019 +0000
  3. 15616b5 dts: arm: socfpga: merge gen5 devicetrees from linux by Simon Goldschmidt · Fri Nov 02 11:54:52 2018 +0100
  4. 3854a1a arm: socfpga: fix device trees to work with DM serial by Simon Goldschmidt · Mon Aug 13 21:34:33 2018 +0200
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. feaa3f9 dts: cadence_spi: Sync DT bindings with Linux by Jason Rush · Tue Jan 23 17:13:10 2018 -0600
  7. 72887e3 arm: socfpga: Fix typos in DT files (environmnet -> environment) by Stefan Roese · Mon Apr 18 14:22:04 2016 +0200
  8. 85e8439 arm: socfpga: sr1500: Misc updates (SPI speed, env location) by Stefan Roese · Thu Mar 03 16:57:39 2016 +0100
  9. bf5ed2e arm: socfpga: Add SoCFPGA SR1500 board by Stefan Roese · Wed Nov 18 11:06:09 2015 +0100