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git01.mediatek.com / filogic / uboot / 9ceda68ea3ddf04a57f9017116402ca819abb462 / drivers / clk / rockchip / clk_rk3588.c
  1. 2892074 clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent by Elaine Zhang · Thu Oct 12 18:18:12 2023 +0800
  2. 9aaa5ab clk: rockchip: rk3588: support aclk_top_root set 750M by Elaine Zhang · Wed Oct 11 18:29:45 2023 +0800
  3. 63f88d1 clk: rk3588: Add 742.5M parameter for PLL by Guochun Huang · Wed Oct 11 18:29:44 2023 +0800
  4. 2f55082 reset: rockchip: implement rk3588 lookup table by Eugen Hristev · Mon May 15 13:55:04 2023 +0300
  5. 3d3f407 clk: rockchip: rk3588: add hardcoded assigned clocks values by Eugen Hristev · Thu Apr 13 14:36:45 2023 +0300
  6. f179826 clk: rockchip: correct trivial typo in debug message by Eugen Hristev · Tue Apr 11 10:17:56 2023 +0300
  7. 291343a clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support by Jonas Karlman · Tue Apr 18 16:46:42 2023 +0000
  8. b450590 rockchip: rk3588: Add support for sdmmc clocks in SPL by Jonas Karlman · Mon Apr 17 19:07:20 2023 +0000
  9. 5515223 clk: rockchip: rk3588: Fix clk_aux16m in clock driver by Jonas Karlman · Tue Mar 14 00:38:27 2023 +0000
  10. 7d031ee clk: rockchip: Add rk3588 clk support by Jagan Teki · Mon Jan 30 20:27:36 2023 +0530