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git01.mediatek.com / filogic / uboot / 9c88912198909ca5718266540e740bb42b32e32d / drivers / ddr / altera / sdram_agilex.c
  1. 9558862 dm: Use access methods for dev/uclass private data by Simon Glass · Tue Dec 22 19:30:28 2020 -0700
  2. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  3. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  4. f7ed78b treewide: convert bd_t to struct bd_info by coccinelle by Masahiro Yamada · Fri Jun 26 15:13:33 2020 +0900
  5. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  6. f11478f common: Move hang() to the same header as panic() by Simon Glass · Sat Dec 28 10:45:07 2019 -0700
  7. 7ead421 ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access by Thor Thayer · Fri Dec 06 13:47:32 2019 -0600
  8. 4ddb909 ddr: altera: agilex: Add SDRAM driver for Agilex by Ley Foon Tan · Wed Nov 27 15:55:27 2019 +0800