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git01.mediatek.com / filogic / uboot / 9a9dc1dc1fec43eee4f9292ad939ec10a4cad607 / arch / arm / mach-socfpga / wrap_sdram_config.c
  1. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  2. 372f70d arm: socfpga: Switch to filtered QTS files by Marek Vasut · Mon Aug 10 21:21:07 2015 +0200
  3. aefb78d arm: socfpga: Move wrappers into platform directory by Marek Vasut · Sun Aug 02 21:12:09 2015 +0200[Renamed (98%) from board/altera/socfpga/wrap_sdram_config.c]
  4. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  5. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  6. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  7. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  8. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200