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git01.mediatek.com / filogic / uboot / 98a2a7af5db73bc130cc6de1cf2769659072e736 / board / freescale / mpc8544ds / ddr.c
  1. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · Mon Jan 31 22:18:47 2011 -0600
  2. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  3. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  4. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  5. 573ad30 FSL DDR: Convert MPC8544DS to new DDR code. by Kumar Gala · Tue Aug 26 08:02:30 2008 -0500