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git01.mediatek.com / filogic / uboot / 9100c0fd11f8b9c85f6b52b5c50497b1b607d40a / arch / arm / mach-uniphier / ddrphy / ddrphy-training.c
  1. 9100c0f ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_* by Masahiro Yamada · Wed Dec 16 10:42:29 2015 +0900
  2. be5b847 ARM: uniphier: add const qualifier to constant array by Masahiro Yamada · Wed Dec 16 10:36:13 2015 +0900
  3. 75f16f8 ARM: uniphier: allow to enable multiple SoCs by Masahiro Yamada · Tue Sep 22 00:27:39 2015 +0900[Renamed from arch/arm/mach-uniphier/ddrphy_training.c]
  4. 9937245 ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefs by Masahiro Yamada · Fri May 29 17:30:04 2015 +0900
  5. 663a23f ARM: UniPhier: replace <asm/io.h> with <linux/io.h> by Masahiro Yamada · Fri May 29 17:30:00 2015 +0900
  6. 95387e2 ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h> by Masahiro Yamada · Fri Feb 27 02:26:44 2015 +0900
  7. f856398 ARM: UniPhier: move SoC sources to mach-uniphier by Masahiro Yamada · Fri Feb 27 02:26:42 2015 +0900[Renamed from arch/arm/cpu/armv7/uniphier/ddrphy_training.c]
  8. 04191e5 ARM: UniPhier: add DDR PHY training code by Masahiro Yamada · Fri Dec 19 20:20:52 2014 +0900