Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 90f903b67985062f6203506accfd5ca12457bb5a / drivers / clk / clk_stm32h7.c
  1. 78df577 clk: clk_stm32h7: Fix prescaler for Domain 3 by Patrice Chotard · Wed Feb 07 10:44:48 2018 +0100
  2. 5301635 clk: clk_stm32h7: Fix stm32_clk_get_rate() for timer by Patrice Chotard · Wed Feb 07 10:44:47 2018 +0100
  3. 789ee0e stm32: fix STMicroelectronics copyright by Patrice Chotard · Mon Oct 23 09:53:58 2017 +0200
  4. aa69ee5 dm: clk: fix PWR_CR3 register's bit 2 name by Patrice Chotard · Mon Oct 09 11:41:24 2017 +0200
  5. bb698ea dm: clk: remove CLK() macro for clk_stm32h7 by Patrice Chotard · Mon Oct 09 11:41:23 2017 +0200
  6. 81e1042 treewide: replace with error() with pr_err() by Masahiro Yamada · Sat Sep 16 14:10:41 2017 +0900
  7. 5fffeab dm: clk: add clk driver support for stm32h7 SoCs by Patrice Chotard · Wed Sep 13 18:00:06 2017 +0200