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git01.mediatek.com / filogic / uboot / 907975adcaa00da9d7301e22c72ad99f608e8bda / board / freescale / mpc8610hpcd / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  3. 54634b4 FSL DDR: Convert MPC8610HPCD to new DDR code. by Jon Loeliger · Tue Aug 26 15:01:36 2008 -0500