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git01.mediatek.com / filogic / uboot / 8e9c4fdc213c67c2d0b4a64deba338fdb9d27e1a / arch / arm / cpu / armv7 / sunxi / dram.c
  1. 8e9c4fd sunxi: dram: Improve DQS gate data training error handling by Siarhei Siamashka · 10 years ago
  2. 020a634 sunxi: dram: Use divisor P=1 for PLL5 by Siarhei Siamashka · 10 years ago
  3. 586757a sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) by Siarhei Siamashka · 10 years ago
  4. 3ad063a sunxi: dram: Re-introduce the impedance calibration ond ODT by Siarhei Siamashka · 10 years ago
  5. 72ed869 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions by Siarhei Siamashka · 10 years ago
  6. d89297a sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i by Siarhei Siamashka · 10 years ago
  7. 6f66418 sunxi: dram: Remove broken impedance and ODT configuration code by Siarhei Siamashka · 10 years ago
  8. ce4d21c sunxi: dram: Fix CKE delay handling for sun4i/sun5i by Siarhei Siamashka · 10 years ago
  9. a1d9f03 sunxi: dram: Respect the DDR3 reset timing requirements by Siarhei Siamashka · 10 years ago
  10. 551bfb9 sunxi: dram: Remove broken super-standby remnants by Siarhei Siamashka · 10 years ago
  11. 27942f1 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function by Siarhei Siamashka · 10 years ago
  12. 8c1c782 sunxi: Add sun5i support by Hans de Goede · 10 years ago
  13. 3ab9c23 sunxi: Add sun4i support by Hans de Goede · 10 years ago
  14. 2f1afcc sunxi: add sun7i dram setup support by Ian Campbell · 11 years ago