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git01.mediatek.com / filogic / uboot / 8d7b6a86c1605e996b8806386606abc944ba4a08 / drivers / fpga / versalpl.c
  1. c0806cc fpga: xilinx: pass compatible flags to load() callback by Oleksandr Suvorov · Fri Jul 22 17:16:10 2022 +0300
  2. 0768aeb xilinx: zynqmp: synchronize firmware call return payload by Ibai Erkiaga · Tue Aug 04 23:17:26 2020 +0100
  3. 274410a arm64: xilinx: Print fpga error value in hex by T Karthik Reddy · Thu May 14 07:49:36 2020 -0600
  4. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  5. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  6. 6333448 common: Move ARM cache operations out of common.h by Simon Glass · Thu Nov 14 12:57:39 2019 -0700
  7. 142fb5b arm64: versal: Rename versal_pm_request to xilinx_pm_request by Michal Simek · Fri Oct 04 15:52:43 2019 +0200
  8. 81efd2a arm64: xilinx: Move firmware functions from platform to driver by Michal Simek · Fri Oct 04 15:45:29 2019 +0200
  9. b739897 arm64: versal: fpga: Add PL bit stream load support by Siva Durga Prasad Paladugu · Mon Aug 05 15:54:59 2019 +0530