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git01.mediatek.com / filogic / uboot / 868ba89f692af4794b96d1767e8cdbcf6b5c8ed3 / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c
  1. 645d4d5 sunxi: Fix PLL1 running at half speed on sun8i by Hans de Goede · Sat Dec 27 17:56:59 2014 +0100
  2. 0bfa774 sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them by Hans de Goede · Sun Dec 07 21:09:31 2014 +0100
  3. 0cbc4cb sun6i: Add a sigma_delta_enable paramter to clock_set_pll5() by Hans de Goede · Sun Nov 30 11:58:17 2014 +0100
  4. 70d7ab5 sunxi: Add video pll clock functions by Hans de Goede · Sat Nov 08 14:07:27 2014 +0100
  5. c27d68d sun6i: Add clock functions needed for SPL / DRAM init by Hans de Goede · Sat Oct 25 20:16:33 2014 +0200
  6. 6ee6388 ARM: sunxi: Add support for using R_UART as console by Chen-Yu Tsai · Wed Oct 22 16:47:47 2014 +0800
  7. 3a04542 ARM: sun6i: Add clock support by Chen-Yu Tsai · Fri Oct 03 20:16:25 2014 +0800