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git01.mediatek.com / filogic / uboot / 8358d59f734fdfa80141806752237d7873f279a4 / cpu / mpc8xxx
  1. 36a6843 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). by Poonam Aggrwal · Thu Sep 03 19:42:40 2009 +0530
  2. 4ca72ae ppc/85xx/86xx: Device tree fixup for number of cores by Poonam Aggrwal · Wed Sep 02 19:40:36 2009 +0530
  3. da6e1ca ppc/85xx,86xx: Handling Unknown SOC version by Poonam Aggrwal · Wed Sep 02 13:35:21 2009 +0530
  4. 666ced1 ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host by Kumar Gala · Wed Sep 02 09:03:08 2009 -0500
  5. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  6. 13e21b1 85xx: Added single core members of FSL P1xx/P2xx processors series by Poonam Aggrwal · Thu Aug 20 18:57:45 2009 +0530
  7. dfe86a7 85xx: Added P1020 Processor Support. by Poonam Aggrwal · Fri Jul 31 12:08:27 2009 +0530
  8. 4baef82 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx by Poonam Aggrwal · Fri Jul 31 12:08:14 2009 +0530
  9. 9120884 8xxx: Refactored common cpu specific code for 85xx/86xx into one file. by Poonam Aggrwal · Fri Jul 31 12:07:45 2009 +0530
  10. f4018f9 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · Fri Jul 17 10:14:48 2009 -0500
  11. efb8ce3 fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · Wed Jul 01 16:51:59 2009 -0500
  12. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  13. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  14. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  15. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · Tue Feb 10 23:53:40 2009 -0600
  16. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
  17. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  18. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  19. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  20. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  21. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  22. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  23. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  24. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  25. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  26. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  27. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  28. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  29. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:32 2008 -0500
  30. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:30 2008 -0500
  31. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500