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git01.mediatek.com / filogic / uboot / 82568300e4ee3e269fb90c62fe3a20f585f68f1b / drivers / clk / exynos / clk-pll.h
  1. 6211235 clk: exynos: Fix incorrect clock lookup for non-top CMUs by Sam Protsenko · Thu Mar 07 20:18:57 2024 -0600
  2. 49ba25a clk: exynos: Don't expose prototypes for not used functions by Sam Protsenko · Thu Mar 07 20:18:56 2024 -0600
  3. 8a0f634 clk: exynos: Add Samsung clock framework by Sam Protsenko · Wed Jan 10 21:09:03 2024 -0600
  4. 8bcc884 clk: exynos: Move pll code into clk-exynos7420 by Sam Protsenko · Wed Jan 10 21:09:02 2024 -0600
  5. 0f3bda0 clk: exynos: Add header guard for clk-pll.h by Sam Protsenko · Tue Nov 07 15:22:00 2023 -0600
  6. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  7. e3fc84c clk: exynos: add clock driver for Exynos7420 Soc by Thomas Abraham · Sat Apr 23 22:18:09 2016 +0530